Posts Tagged ‘debug’

FRDM K64F Printf to UART using Processor Expert

05/06/2015 4 comments

If you are using the OpenSDAv2 USB for debugging with Segger J-Link on the FRDM K64F development board within Eclipse then you may want to route Printf functions to the Segger virtual com port. This blog will cover how to set this up on Windows using Processor Expert on KSDK 1.2.0 and Eclipse Luna.


  1. Prerequisites
  2. Create New Project
  3. Configure Processor Expert
  4. Hello World Test Code
  5. View output using COM port terminal application
  6. Clock Configuration


Before you begin please make sure your development environment is setup and you can already compile and debug code using KSDK 1.2.0 on Eclipse Luna. If not please refer to my blog: Toolchain: KSDK 1.2.0 with Eclipse 4.4 (Luna) and GNU ARM Plugin

Create New Project

  1. Within Eclipse, on the top menu point your mouse over “File” menu item, this should expand out with an option to select “Kinetis Project”.NewKinetisProject
  2. Name your project, I tend to name my project starting with the type of development board or processor followed by an underscore and then purpose of the project, this allows me to create projects of the same purpose for other boards/processors. Set location of project, I use the default location under the workspace area. Click Next.NameProject
  3. Select the development board used, and click Next.DevelopmentBoard
  4. Select “KSDK 1.2.0”.
    Set location to KSDK path, I use an absolute path but you can select Environment variable if you have set up a path under Windows operating system environment variables with a name called “KSDK_PATH” that points to the location of the KSDK folder. The location of my KSDK is in the default location where KSDK would install to.
    Ensure “Processor Expert” checkbox is checked. The perspective radio button you select does not matter nor does the Project mode for this project.
    Click the Next button.SDKandPESelect
  5. Select “GNU C Compiler” and Click the “Finish” button.SelectGNUCompilerN.B. Wait a while for Processor Expert to finish generating the initial source for the project. Keep an eye on the progress when it reaches 100% by looking at the bottom right hand corner of Eclipse.GeneratingCode

Configure Processor Expert

Before you proceed make sure you can build the project now without errors. If not then make sure you have followed the instructions and understood how to setup your Eclipse environment as specified in the blog Toolchain: KSDK 1.2.0 with Eclipse 4.4 (Luna) and GNU ARM Plugin, especially the “Setting Eclipse workspace preferences” section.

  1. Open the Processor Expert perspective, this should be a button on the top right hand side of Eclipse.OpenPEPerspectiveIf it’s not there, try clicking on the “Open Perspective” button and then selecting “Processor Expert” in the form that appears.OpenPerspective


  2. Click on the “Components Library” tab, search for the component “fsl_debug_console” and double click on it.addcomponent_debugConsole
  3. Select the “DbgCs1:fsl_debug_console” in the Components windowComponent_DbgCs1
  4. Click on the “Component Inspector” tab. Then click on the three ellipses “…” button next to the Baud rate.Component_DbgCs1_BaudRate_ElipsesButton
  5. Double click on the baud rate “115200” on the right hand form and click the “OK” button.SetBaudRateNote: Note that “Clock cfg. 4” is Enabled above. We will review these settings further down in “Clock Configuration”.
  6. On the Pin Settings tab, the FRDM K64F board uses Port B 16 (PTB16) for RxD and Port B 17 (PTB17) for TxD. Make sure these are set correctly.  You can refer to the FRDM-K64F Freedom Module User’s Guide at section “11 Serial port” for these pin settings.PinSetting
  7. Make sure all component settings are saved and click on the “Generate Processor Expert Code” button within the Components window.GenerateCode

Hello World Test Code

Make sure your project can still build without errors at this point. Then open the “main.c” file, search for the text that says “/* Write your code here */” and “/* For example: for(;;) { } */” and just below it write the following code:

PRINTF(“Hello World”);


Note: PRINTF should intentionally be uppercase. This will use a printf function supplied with the KSDK.
That’s all there is to it Smile
Build your project again, it should compile without Errors.

View output using COM port terminal application

To be able to view the output of the PRINTF statement you will need a serial port terminal application. There are several good ones available for Windows but one I like to use which has other useful features available is an application called “PuTTY”. You can download the latest copy at:


You are going to need the COM Port used by your device. You can find out what yours is by opening the Windows “Device Manager” and expanding the “Ports (COM & LPT)” section. Look for the device named “JLink CDC UART Port” and in brackets you can see the COM port used.


After downloading the PuTTY file, simply run the downloaded file. Select the “Serial” radio button, in the “Serial line” text box type the COM port used by your JLink CDC UART Port, in my case its “COM3”.


One set, click the Open button. You should see a blank terminal window.


Now go back to Eclipse and run the application, you should now see the following in the PuTTY terminal window:


Clock Configuration

Congratulations if all is working well for you now. I wanted to point out what the clock configuration is that gets used. This is helpful to know if for some reason you do not have or are using the default clock settings.

If you refer to section “52.4.3 Baud rate generation” within the K64 reference manual K64P144M120SF5RM, we can see the Baud rate is a calculation of the following:

UART baud rate = UART module clock / (16 × (SBR[12:0] + BRFD))

  • UART module clock: is one of 5 clock configuration sources we can choose from set on the clock manager.
  • SBR: is a module clock divisor we use that can be a number between 1 and 8191.
  • BRFD: is a fractional fine-adjust counter that adds fractional delays to the baud rate clock to allow fine trimming of the baud rate to match the system baud rate. Basically any fraction by 32 bits (n/32).

Lets take a look at the clock manager to see what the settings are in this example. Go into the Processor Expert perspective. Select the “clockMan1:fsl_clock_manager” component in the Components window.


In the Component Inspector window, select the “Clock settings tab” then the “Clock sources” tab. Take note of the clock frequency  under the System oscillator 0 section.


Now click on the “Clock configuration” tab then select the “MCG settings” tab. Now select the “clockMan1_InitConfig4” configuration which is the one we used for the “DbgCs1:fsl_debug_console” configuration. Note we are using System oscillator 0 here and the MCG mode is “PEE” which uses PLL settings, so looking at the PLL settings we can see 48 MHz is entered as the desired output clock.


Now select the tab “System clocks” tab. If we refer to section “5.7.10 UART clocking” within the K64 reference manual K64P144M120SF5RM, we can see that UART0 uses the core/system clock which should be set to 48 MHz.


Ok, so coming back to the baud rate formula:

UART baud rate = UART module clock / (16 × (SBR[12:0] + BRFD))

    115,200 Hz = 48 MHz (or 48,000,000 Hz) / (16 × (SBR[12:0] + BRFD))

16 × (SBR[12:0] + BRFD) = 48,000,000 Hz / 115,200 Hz

16 × (SBR[12:0] + BRFD) = 416.6666666666667

(SBR[12:0] + BRFD) = 416.6666666666667 / 16

(SBR[12:0] + BRFD) = 26.04166666666667

So therefore SBR can equal 26

BRFD can be calculated as 0.04166666666667 * 32 = 1.333333333333333 but must be rounded to a whole number thus = 1.


Ok so maybe that’s a lot of detail on the calculation but I hope this helps when you are trying to use different clock settings.